| title | media type | ISBN-13 | year of publica- tion | other author(s) |
|---|---|---|---|---|
| Verification Methodology Manual for Low Power | Paperback | 978-1-60743-413-9 | 2009 | Srikanth Jadcherla · Yoshio Inoue · David Flynn |
| Verification Methodology Manual for SystemVerilog | " | 978-1-4614-9813-1 | 2014 | |
| Verification Methodology Manual for Systemverilog | Broschiert | 978-0-387-50645-6 | 2008 | Eduard Cerny · Alan Hunter |
| Verification Methodology Manual for SystemVerilog | Hardcover | 978-0-387-25538-5 | 2005 | Eduard Cerny · Alan Hunter · Andy Nightingale |
| Writing Testbenches: Functional Verification of HDL Models, 2nd ed. | Paperback | 978-81-8128-566-9 | ||
| Writing Testbenches: Functional Verification of HDL Models | Hardcover | 978-1-4020-7401-1 | 2003 | |
| Writing Testbenches: Functional Verification of HDL Models | " | 978-0-7923-7766-5 | 2000 | |
| Writing Testbenches using SystemVerilog | Paperback | 978-1-4419-3978-4 | 2010 | |
| Writing Testbenches using SystemVerilog | Hardcover | 978-0-387-29221-2 | 2006 | |
| ベリフィケーション・メソドロジ・マニュアル―SystemVerilogでLSI機能検証プロセスを徹底改善 berifuikeーshon・mesodoroji・manyuaru―SystemVerilogdeLSIkinoukenshoupurosesuwotetteikaizen | 単行本 | 978-4-7898-3615-9 | 2006 | Alan Hunter · Eduard Cerny · Andrew Nightingale |