| title | ISBN-13 (ISBN-10) | year of publica- tion | other author(s) |
|---|---|---|---|
| Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench: The System Architect's Workbench | 978-0-7923-9053-4 (0-7923-9053-9) | 1989 | Elizabeth D. Lagnese · Robert A. Walker · Jayanth V. Rajan · Robert L. Blackburn · John A. Nestor |
| The Verilog® Hardware Description Language | 978-1-4020-7089-1 (1-4020-7089-6) | 2002 | Philip R. Moorby |
| The Verilog® Hardware Description Language | 978-0-7923-8166-2 (0-7923-8166-1) | 1998 | " |
D. T. · D. Thomas · Donald E. · Donald E. Thomas Jr. MD FACP FACR · Donald Thomas · E.T. · E. Thomas