| title | ISBN-13 | year of publica- tion | other author(s) |
|---|---|---|---|
| Verification Methodology Manual for Low Power | 978-1-60743-413-9 | 2009 | Srikanth Jadcherla · Yoshio Inoue · David Flynn |
| Verification Methodology Manual for SystemVerilog | 978-0-387-25538-5 | 2005 | Eduard Cerny · Alan Hunter · Andy Nightingale |
| Writing Testbenches - Functional Verification of HDL Models | 978-0-7923-7766-5 | 2000 | |
| Writing Testbenches: Functional Verification of HDL Models, Second Edition | 978-1-4020-7401-1 | 2003 | |
| Writing Testbenches using SystemVerilog | 978-0-387-29221-2 | 2006 | |